module LFSR(
	input  [7:0] in,
	input        clock,
	input        reset,
	output [7:0] out
);

	reg [7:0] registers;

	always @(posedge clock or negedge reset) begin
		if(reset == 1) begin // set initial value to registers
			registers <= in;
		end else begin
			if(registers == 0) // if registers is zero, set registers to 1;
				registers <= 8'b0000_0001;
			else begin
				registers <= {registers[4]^registers[3]^registers[2]^registers[0], registers[7:1]};
			end
		end
	end

	assign out = registers;

endmodule
